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HMD16M32M8GH
64Mbyte (16Mx36) FP Mode 4K Ref. 72pin-SIMM Design Part No. HMD16M32M8GH GENERAL DESCRIPTION
The HMD16M32M8GH is a 16M x 32bit dynamic RAM high-density memory module. The module consists of eight CMOS 16M x 4bit DRAMs in 32-pin SOJ or TSOP packages mounted on a 72-pin glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a Single In-line Memory Module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible.
FEATURES
wPart Identification HMD16M32M8GH ---4K Cycles/64ms Ref, Gold w Access times : 50, 60ns w High-density 64MByte design w Single + 5V 0.5V power supply w JEDEC standard Pdpin & pinout w TTL compatible inputs and outputs w/CAS-before-/RAS & Hidden Refresh capability w/RAS-only refresh capability wFast Page Mode Operation PIN 1 2 3 4 5 6 7 8 9 10 11 12 -5 -6 M 13 14 15 16 17 18 tRC 90ns 110ns SYMBOL Vss DQ0 DQ18 DQ1 DQ19 DQ2 DQ20 DQ3 DQ21 Vcc NC A0 A1 A2 A3 A4 A5 A6 PIN 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
PIN ASSIGNMENT
SYMBOL A10 DQ4 DQ22 DQ5 DQ23 DQ6 DQ24 DQ7 DQ25 A7 A11 Vcc A8 A9 NC /RAS2 NC NC PI N 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 SYMBOL NC NC Vss /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 NC NC /W NC DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 PI N 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 SYMBO L DQ12 DQ30 DQ13 DQ31 Vcc DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 NC PD1 PD2 PD3 PD4 NC Vss
OPTIONS
w Timing 50ns access 60ns access w Packages 72-pin SIMM
MARKING
PERFORMANCE RANGE
Speed 5 6 tRAC 50ns 60ns tCAC 13ns 15ns
PRESENCE DETECT PINS
Pin PD1 PD2 PD3 PD4 50ns Vss NC Vss Vss 60ns Vss NC NC NC
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FUNCTIONAL BLOCK DIAGRAM
DQ0-DQ35
HMD16M32M8GH
/CAS0 /RAS0
CAS CAS RAS RAS OE W W OE
U0 U1
DQ0 DQ0-DQ3 DQ1 DQ2 A0-A11 A0-A11 DQ3 DQ0 DQ4-DQ7 DQ1 DQ2 A0-A11 A0-A11 DQ3 D DQ8 Q
/CAS2 /RAS2
CAS RAS OE W
U7 DQ18-DQ21
A0-A11
CAS CAS RAS RAS OE W W OE
U2 U1
CAS RAS OE W
U8 DQ22-DQ25
A0-A11
CAS CAS RAS W RAS W
U2 U10
A0-A11 A0-A11
CAS RAS
U3
W A0-A11
DQ26
/CAS1
CAS CAS RAS RAS OE W OE W
DQ0 U0 DQ9-DQ12 U5 DQ1 A0-A11 A0-A11 DQ2 DQ3
/CAS3
CAS RAS OE W
U11
DQ27-DQ30
A0-A11
CAS CAS RAS RAS OE W OE W
DQ0 U1 DQ13-DQ16 U6 DQ1 A0-A11 A0-A11 DQ2 DQ3 D DQ17 Q
CAS RAS OE W
U12
DQ31-DQ34
A0-A11
CAS CAS RAS W RAS W
U9 U2
A0-A11 A0-A11
CAS RAS
U4
W A0-A11
DQ35
/W A0-A11
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ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN ,OUT Vcc PD TSTG
HMD16M32M8GH
RATING -1V to 7.0V -1V to 7.0V 12W -55oC to 125oC
Short Circuit Output Current IOS 50mA w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
( Voltage reference to VSS, TA=0 to 70 o C ) PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage SYMBOL Vcc Vss VIH VIL MIN 4.5 0 2.4 -1.0 TYP. 5.0 0 MAX 5.5 0 Vcc 0.8 UNIT V V V V
DC AND OPERATING CHARACTERISTICS
SYMBOL ICC1 -6 ICC2 ICC3 -6 -5 ICC4 -6 ICC5 ICC6 -6 Il(L) IO(L) VOH VOL ICC1 : Operating Current * (/RAS , /CAS , Address cycling @tRC=min.)
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SPEED -5
MIN -10
MAX 1080 960 24 1080 960 840 600 12 1080 960 10 5 2.4 0.4
UNITS mA mA mA mA mA mA mA mA mA mA A A V V
Don't care -5
Don't care -5
Don't care -5
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ICC2 : Standby Current ( /RAS=/CAS=VIH ) ICC3 : /RAS Only Refresh Current * ( /CAS=V IH, /RAS, Address cycling @tRC=min ) ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min ) ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V ) ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min ) IIL : Input Leakage Current (Any input 0V VIN 6.5V, all other pins not under test = 0V) IOL : Output Leakage Current (Data out is disabled, 0V VOUT 5.5V VOH : Output High Voltage Level (IOH= -5mA ) VOL : Output Low Voltage Level (IOL = 4.2mA )
HMD16M32M8GH
* NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle.
CAPACITANCE
( TA=25 C, Vcc = 5V, f = 1Mz ) SYMBOL CIN1 C IN2 CIN3 CIN4 CDQ1 MIN MAX 50 66 38 24 17 UNITS pF pF pF pF pF
o
DESCRIPTION Input Capacitance (A0-A11) Input Capacitance (/W) Input Capacitance (/RAS0) Input Capacitance (/CAS0-/CAS3) Input/Output Capacitance (DQ0-31)
AC CHARACTERISTICS
PARAMETER Random read or write cycle time Access time from /RAS Access time from /CAS Access time from column address /CAS to output in Low-Z Output buffer turn-off delay Transition time (rise and fall) /RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS to /CAS delay time
( 0 C TA 70oC , Vcc = 5V10%, See notes 1,2.) -5 SYMBOL MIN tRC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD 3 3 1 30 50 13 38 8 20 10K 37 10K 13 50 84 50 13 25 3 3 1 40 60 15 45 10 20 10K 45 10K 15 50 MAX MIN 104 60 15 30 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns -6 UNIT
o
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/RAS to column address delay time /CAS to /RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address hold referenced to /RAS Column Address to /RAS lead time Read command set-up time Read command hold referenced to /CAS Read command hold referenced to /RAS Write command hold time Write command hold referenced to /RAS Write command pulse width Write command to /RAS lead time Write command to /CAS lead time Data-in set-up time Data-in hold time Data-in hold referenced to /RAS Refresh period Write command set-up time /CAS setup time (C-B-R refresh) /CAS hold time (C-B-R refresh) /RAS precharge to /CAS hold time Access time from /CAS precharge Fast page mode cycle time /CAS precharge time (Fast page) /RAS pulse width (Fast page ) /W to /RAS precharge time(C-B-R refresh) /W to /RAS hold time (C-B-R refresh) /CAS precharge(C-B-R counter test) NOTES tRAD tCRP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tREF tWCS tCSR tCHR tRPC tCPA tPC tCP tRASP tWRP tWRH tCPT 40 8 50 10 10 20 200K 0 5 10 5 28 45 10 60 10 10 30 15 5 0 10 0 8 50 25 0 0 0 10 50 10 13 8 0 8 50 64 0 5 10 5 25 15 5 0 10 0 10 55 30 0 0 0 10 55 10 10 10 0 10 55
HMD16M32M8GH
30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 64 ns ns ns ns ns 35 ns ns ns 200K ns ns ns ns
1.An initial pause of 200s is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 2TTL loads and 100pF 4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max) limit, then access time is controlled exclusively by t CAC.
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5.Assumes that tRCD tRCD(max)
6. tAR, tWCR, tDHR are referenced to tRAD(max)
HMD16M32M8GH
7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH or VOL. 8. tWCS, tRWD, tCWD anf tAWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristic only. If t WCS tWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in readwrite cycles. 11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA.
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PACKAGING INFORMATION
SIMM Design Unit : mm
HMD16M32M8GH
107.95 0.20
3.38
3.38
27.0 0.2 10.16 6.35
1
71
2.03 1.0 6.35 6.35 95.25 1.27 3.34
Front View
2
72
Back View
0.25
MAX
2.54 MIN
1.27 Gold : 1.040.10 1.27 Solder:0.9140.10
ORDERING INFORMATION
Part Number Density Org. Package Ref. Vcc MODE SPEED
HMD16M32M8GH-5 HMD16M32M8GH-6
64Byte 64Byte
x 32 x 32
72 Pin-SIMM-Gold 72 Pin-SIMM-Gold
4K 4K
5V 5V
FPM FPM
50ns 60ns
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